Digital Logic Sim

A minimalistic digital logic simulator · By Sebastian Lague

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Flickering SR Latch Trouble

A topic by gardrek created Apr 19, 2025 Views: 723 Replies: 11

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gardrek170 days ago (1 edit)

Please excuse my sloppy wiring. I have highlighted in Violet here the offending signal, which flickers in only some instances of this chip.
I don't really understand why this flickering signal is happening. My understanding is that the NAND SR latch should only have a race condition if both the inputs are *high*. Is there some obvious thing I'm doing wrong or some way to fix this? Note that the gray bracket chips just pass the data through, they're just an easy way to re-connect multiple things at once.

gardrek170 days ago

Note that this is on v2.1.2

gardrek170 days ago (1 edit)

No okay, the NAND latch should only be in a race condition if both inputs are *low*, right? It's a NOR latch where the race happens when both inputs are *high*. (not that it should matter in this case, because the two inputs are *different* in this screenshot)

ThatRobHuman170 days ago (1 edit)

Correct

EDIT:

Just so you know there is some known funkiness in the simulation with latches both SR-style and RS-style (or any feedback loop, really) and how their initial starting conditions (which are random) affect their future timing behavior. Sometimes it can take an extra tick to set, sometimes an extra tick to reset. Once the initial state is determined, it will be consistent, but there's no way to determine how it will act before the initial state settles.

Also (and there's some nuance to this that I'm going to skip over) RS latches that exist as their own component will always start Low, but an SR latch's will always start in an unknown state.

also if you use an RS-style latch, and have a NOT gate attached to the output to serve as the Q-compliment, there is a chance that you will have both the Q and the Q-compliment have the same value for one tick.

gardrek170 days ago

Interesting. What do you mean "RS latches that exist as their own component"? Does this mean instancing each latch out into its own chip might solve this issue? I guess it's worth a try.

ThatRobHuman170 days ago (1 edit)

Not so with an SR Latch (aka: a NAND or NOR style latch) but yes with an RS Latch (a Not-or-and style latch).

Either style will still take an extra tick on one of either the SET or RESET action, but an RS it will always start in a low state.

gardrek170 days ago

I see what you mean. However, pulling the latches out into their own chip does seem to have fixed the problem.

pullobi108 days ago

so wait what how does that work

I've been trying this for 2 hours nothing seems to work

can you show me an eaxmple

kshlok102 days ago (1 edit)

I got past the randomness, use a multiplexer. the A input would be the output of the mux (it cycles) and the B input would be the data. the select would be the output. I tested it in Sebastian's RAM-256x8 and got all 0s.

bonico312101 days ago

can you send the truth table . Maby i can make another similar version

kshlok81 days ago

For memory, i dont think a truth table can exist

bonico31281 days ago (1 edit)

why whould we need a NAND latch. I made ram with AND gate OR gate & NOT gate

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Digital Logic Sim

Flickering SR Latch Trouble