itch.io

https://drive.google.com/file/d/1v9hGBByIgiNYAESgUkeYV1ik5it8DZAd/view?usp=shari...

IT HAS R0-R7 GENERAL PURPOSE REG AND 5 GRAPHICS REG (X, Y, R, G AND B).
IT CAN HAVE UP TO  128 INST SET.
YOU MUST USE THIS DLS 2 VERSION: Release DLS Community Edit v1.2.1 · firecerne/Digital-Logic-Sim-Community-Edit.

---------------------------------- ALU_OP ENCODING -----------------------------

   0000 : ADD       0001 : SUB       0010 : AND       0011 : OR

   0100 : XOR       0101 : NOT       0110 : INC       0111 : DEC

   1000 : MUL       1001 : DIV       1010 : MOD       1011 : SHL

   1100 : SHR       1101 : ROL       1110 : ROR       1111 : NEG

SHL/SHR/ROL/ROR: 0-7

================================================================================

I'M NOT REALLY A COMPUTER GUY. I DO IT AS A GAME. 

I CAN SHARE THE FILE AND YOU GUYS CAN MODIFY AND IMPROVE IT: https://drive.google.com/file/d/19L_iY2GA7wIV7NgT5DtGXlwdsDtPnQdO/view?usp=shari...
IT'S A MODIFY VERSION OF PONG! (8-bit computer) - Digital Logic Sim community - itch.io.

https://drive.google.com/file/d/1D-SDzgKlAKT5j60bjaFbWhTuVP_6sAxP/view?usp=drive...

I STILL NEED TO MAKE IMPROVEMENT

---------------------------------- ALU_OP ENCODING -----------------------------

ALU_OP2..ALU_OP0 (Micro B bits 12,11,10):

   000 : ADD

   001 : SUB

   010 : AND

   011 : OR

   100 : XOR

   101 : NOT 

   110 : INC

   111 : DEC 

IT IS 0-3 STEPS. IT IS FETCHED AT STEP 0.

You can create any size of pin/merge&s p lit you want(CTRL+B). The bus automatically updates for each pin created 

It's very simple. Download the OS version(1.1.2) you want and install it.

firecerne/Digital-Logic-Sim-Community-Edit: Community Edition of Digital Logic Sim

https://github.com/firecerne/Digital-Logic-Sim-Community-Edit/releases/tag/v1.1.2

The more components you use, the slower the simulation became. You need to find the perfect steps per clock tick for your project. More component= More steps per clock tick.
You can try to simplify by using less component. Create your chip via nand. Use ROM for decoder, 7 seg disp, etc...That's an 8-bits reg faster than the old ways.

What do y'all think?

negative numbers - Digital Logic Sim community - itch.io

What is the easiest way to build a Stack and implant it on CPU?

Diagram?

Try it now

S= START/STOP
X=ONE STEP
C= CLEAR

The visualization is in HEX code. The steps per clock stick must be at least 7.
It has a multiplication (it also runs division) program on it (Multiplicand=0x000, Multiplier=0x002).
It's better when using HEX format to edit the ROM.
EX: LDX 5= 505 (Three digits. The 1st one is the instruction, and the rest is the data.



https://drive.google.com/file/d/1gX9fHKHZM2ACvy0F13JdNZ6kAkDKj9bM/view?usp=shari...

It's better when buses are used for the outputs

What did you use? How is it possible to run the simulation unless you don't use logic gates as the main...?

https://itch.io/profile/ithurius

The better way is to use a RGD display. It has 8 bits address and 12 bits I/O data color. So, you can use the 8 bits address and 2 colors ( a nibble each) to get 8 bits I/O data line.

Figure-1: J-K FLIP FLOP

Figure-2: D FLIP FLOP 

That's 💥💥🔥🔥🔥🔥🔥

Could you share the file, please?

I think it's because the clock and refresh are wired together. In write mode, if the clock and refresh are wired together (same signal), the RGB display only records the data it receives in real time and erases all received data.

I understand. I should have put an enable pin for the output data in each binary cell. Now, I use RGB display instead. The simulation is still smooth with 64KB RAM

It would be better to use  RGB display. By using two colors, you'll have 256 bytes each RGB  display. 

Here's the new version of my 64KB RAM (8 data lines I/O width.
I'm all ears for any suggestion. The link file also includes a 256B & 4KB RAM.
https://drive.google.com/file/d/1Q2a-aOKt2muEutrpK58V-gP_3YwMc2Mr/view?usp=shari...
I used RGB display.   ...

I'm trying to build a large RAM capacity but the simulation gets slower every time I enhance it. 
I'm stocked in 64KB because I need to pause the simulation for viewing or opening it.
N.B: I use logic gates. the binary cell has 3 inputs {select, data, read/write} 

Here is the file link: https://drive.google.com/file/d/1-1ifys702uznO3xJjQy0-F_d9KnuA7W_/view?usp=drive... 

Thanks for your help.

Hi guys,

I have constructed an SR latch, with its inputs (Set and Reset) connected to control signals and outputs as Q and Q̅. However, I am observing that upon using the chip, the latch does not initialize to a predictable state. Sometimes Q is high, and other times it is low, even though the inputs remain stable and no "illegal state" (S and R both high) is introduced. 

Any advice or guidance you could provide would be greatly appreciated. Please let me know if you need further details or screenshots of the circuit design.

Thank you for your time and support.