Digital Logic Sim

A minimalistic digital logic simulator · By Sebastian Lague

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SR latch unstable state

A topic by Bendy509 created 59 days ago Views: 123 Replies: 2

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Bendy50959 days ago

Hi guys,

I have constructed an SR latch, with its inputs (Set and Reset) connected to control signals and outputs as Q and Q̅. However, I am observing that upon using the chip, the latch does not initialize to a predictable state. Sometimes Q is high, and other times it is low, even though the inputs remain stable and no "illegal state" (S and R both high) is introduced.

Any advice or guidance you could provide would be greatly appreciated. Please let me know if you need further details or screenshots of the circuit design.

Thank you for your time and support.

ThatRobHuman58 days ago

NOR and NAND style SR latches will always start in an unstable state, both in real-life and in the simulation.
NOT-AND-OR style RS latches *can* start in a known state *if* you package it up into its own chip (there's a bit more nuance to this, and there are still some oddities, but they will start in a known state). This normally isn't true in real life, but in the simulation, it works out that way.

You can read up on my explorations of simulation oddities, and how they specifically apply to latches here: https://github.com/SebLague/Digital-Logic-Sim/issues/326 (there's a lot that I "learn" and then "unlearn" through that thread, so I would read it in its entirety)

Bendy50958 days ago

Thanks for your help.

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Digital Logic Sim

SR latch unstable state