NOR and NAND style SR latches will always start in an unstable state, both in real-life and in the simulation.
NOT-AND-OR style RS latches *can* start in a known state *if* you package it up into its own chip (there's a bit more nuance to this, and there are still some oddities, but they will start in a known state). This normally isn't true in real life, but in the simulation, it works out that way.
You can read up on my explorations of simulation oddities, and how they specifically apply to latches here: https://github.com/SebLague/Digital-Logic-Sim/issues/326 (there's a lot that I "learn" and then "unlearn" through that thread, so I would read it in its entirety)