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Digital Logic Sim

​A minimalistic digital logic simulator · By Sebastian Lague

what is the most effecient memory design

A topic by goADX created 40 days ago Views: 291 Replies: 7
Viewing posts 1 to 5

i am getting 70 steps per second my whole project is slow i only have 256 bytes of memory with a couple of 1 bytes here and there so what is the most effecient way to make memory/ram

(i think the simulation could have some multithreading but idk)

The better way is to use a RGD display. It has 8 bits address and 12 bits I/O data color. So, you can use the 8 bits address and 2 colors ( a nibble each) to get 8 bits I/O data line.

Or you can use the extra color channel for the instruction, so you can free bits for your data.

the good thing about this ram is that it starts empty, unlike normal d-latch-grid or grid of registers.

But if you want to make it real, RGB display is nonsense.  You can make a RAM with so many and gates and not gates. For 2^n bytes. There will be n registers, n not gates and 2n ands. If you make and gates with tri-state buffers, it will be faster. But this will be maybe more complex than version with decoders. I recommend Sebastian's RAM in his latest video.

I did a 65536 Bytes Ram.

What did you use? How is it possible to run the simulation unless you don't use logic gates as the main...?

RBG. like they said. same structure as Sebastians ram video just with an address