I'm trying to build a large RAM capacity but the simulation gets slower every time I enhance it.
I'm stocked in 64KB because I need to pause the simulation for viewing or opening it.
N.B: I use logic gates. the binary cell has 3 inputs {select, data, read/write}
Here is the file link: https://drive.google.com/file/d/1-1ifys702uznO3xJjQy0-F_d9KnuA7W_/view?usp=drive...
Viewing post in Gigabytes of RAM are now possible
Output can only have one connection , and you use OR gates , but if you use 3 state buffer you can make 3 type of signals [1 0 no connection] no connection allow you connect multiple signals to output BUT only one can be on !!!
if you have 8 cell memory you only need 8 3 state buffer (one per cell) address pin connect to enable data to IN and finally you will get a some extra steps in simulation =D
if You want I can send you my realisation of RAM