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(1 edit)

I'm trying to build a large RAM capacity but the simulation gets slower every time I enhance it. 
I'm stocked in 64KB because I need to pause the simulation for viewing or opening it.
N.B: I use logic gates. the binary cell has 3 inputs {select, data, read/write} 

Here is the file link: https://drive.google.com/file/d/1-1ifys702uznO3xJjQy0-F_d9KnuA7W_/view?usp=drive... 

Because you use to many gates in your RAM for example you use 16 OR this is 15 * 3 gates = 45 gates , if you will use 3 state buffer you don`t need use OR

Deleted 248 days ago

Output can only have one connection , and you use OR gates , but if you use 3 state buffer you can make 3 type of signals [1 0 no connection] no connection allow you connect multiple signals to output BUT only one can be on !!!
if you have 8 cell memory you only need 8 3 state buffer (one per cell) address pin connect to enable data to IN and finally you will get a some extra steps in simulation =D
if You want I can send you my realisation of RAM

I understand. I should have put an enable pin for the output data in each binary cell. Now, I use RGB display instead. The simulation is still smooth with 64KB RAM

I didn't use logic gates and used rgb screen instead and I got to 1mb of storage, but it brings me down to ~1500 steps per second