are you doing it with 16-bits or 24. also its how may regs 3? 2? 12?
N-16 is a 16-bit CISC CPU that has 8 registers, in this fibonacci programm only 4 registers were used. I can share the files of the project if needed.
WARNING: if you want to download the project then you should know that because of DLS bottlenecking the counters (CU, PC, QUEUE) are not guaranteed to always work, I am searching on how to fix that issue, last time I did make stable counter but it made the whole CPU to halt or to CU miss some T-states.