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IDK, now it can count 23 fibonacci numbers and extra 24th overflowed one in 5~ seconds before HALTing (It's was programmed to count 24) and the clock speed is 1.8~ Khz (3700~ steps per second), however it is unstable because of counters, I will try to fix it but if the counters load then the CPU runs flawlessly. And the CPU needs 2 words (3 if MOV reg, addr) and overall 4 processes (Fetch, Fetch, Fetch or ignore, Execute). I could share it in other platforms if needed, overall the ROM itself has 15 / 20 words (I dont remember exactly how much) overall with values in other addresses to test MOV reg, addr.

The big jump will be N-86, but its progress has been frozen due to DLS bottlenecking itself and it runs slowly and it is the reason why I can't even test it, there is another project N-16-E to enchant N-16.

are you doing it with 16-bits or 24. also its how may regs 3? 2? 12?

N-16 is a 16-bit CISC CPU that has 8 registers, in this fibonacci programm only 4 registers were used. I can share the files of the project if needed.

WARNING: if you want to download the project then you should know that because of DLS bottlenecking the counters (CU, PC, QUEUE) are not guaranteed to always work, I am searching on how to fix that issue, last time I did make stable counter but it made the whole CPU to halt or to CU miss some T-states.

Yes please

Latest patch. N-16

https://drive.google.com/file/d/1ejTRkJdJLu2rO5DytLyy1OlfU_tA7kJX/view?usp=drive...

thanks!