Ah, I see what you mean. I already redesigned this though. I do like to optimize for minimal NAND gates but I also like to aim for clarity too, so it's a balance.
the new layout: 
Interesting use of tri-state buffers. Good if you're going for absolute optimization of gate numbers. Actually, in the context of the rest of the circuit you could possibly take it even further, by using active-low inputs for the ripple signals. and maybe even removing the inverters on the display ROM.