But first You must optimize your current logic for example You use a lot of XOR / EOR , but if I good remember you made it from 2 not one AND and 3 other gate but You can make it use only 4 NAND , less gates = quicker simulation , and one more the simulation see user use a special gate for example AND gate so simulation must stop and load AND gate simulate them back to current simulation, but if you use NAND the simulation don`t must stop because you will use basic brick
XD I understood You , now I almost done ALU in mos6502 but I use only NAND some times looks like a pasta , BUT WORK as well XP
About RAM Use RGB 8pin for address and 2x4 bit for data (more data in one place ) and if you use only data without address You will got a register ( Load pin conect to save refresh and clock , Read use 2 4to1 bit and use 8 3state buffer)