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Digital Logic Sim

​A minimalistic digital logic simulator · By Sebastian Lague

Issue with RGB Display

A topic by Hahoolah created 40 days ago Views: 144 Replies: 8
Viewing posts 1 to 6

Hey guys! 

So I've just gotten into this and I'm playing around with the RGB Display, but I get this weird banding pattern and I don't know what's causing it:

I'm currently cycling through all addresses from 0 to 255 and assigning a pure white colour, but every few steps it'll select an already filled-in pixel to fill again. (I verified this by changing the colour being assigned every few pixels.) 

I would understand getting this error if my counter didn't work, but I've verified that it counts correctly by stepping through each clock cycle to check the output number.

Is this a bug with the display or am I misunderstanding something?

Thanks in advance!

(And now that I've written this out one single pixel that normally isn't filled out somehow was lmao) 

(+1)

Good chance your counter is skipping. It's a common issue in DLS right now. What 'steps per clock' are you running in the settings? Does it still do it if you increase the steps per clock and re-load the chip?

Oh, that would make sense :o Thanks for the response!

I was running with the default settings at 250 steps per clock cycle and 1000 steps per second.
I tried increasing the steps per clock cycle to 500, 1000 and 2000, but all that changed is that the banding pattern changed. I'm wondering if the issue is related to the clock itself... Maybe the screen sometimes updates before the counter, so it gets an old address before the counter has time to give it a new one? With the new speed settings it seems to be a consistent 50/50 if it uses a new or old address, so I feel that might be it?


I simplified the inputs and made the colours dependant on the steps as well, hoping to see if anything was being scrambled or anything, but save for some pixels being drawn out of order it doesn't seem like the colours are wrong. 

I'm stumped.

Alright, I think I fixed it

It seems like it indeed was some weird race condition and/or timing thing. Once I chopped off a piece of the 8-bit counter I used for the address line to introduce a delay in the clock and fiddling with the tick speed settings it finally displayed a full screen of pixels!


Ironically, the physical size of the chips I use also seem to have an effect lol

(+1)

Glad you figured it out. I posted about a similar issue here and there's on on-going discussion about the race condition issue here.

How does the inside your counter look?

(1 edit) (+1)

Gotcha, I'll keep an eye on them :) Thank you!

It's a bodge to say the least, and I have no clue if I named things correctly since I have no electical engineering knowledge at all, so don't get your hopes up lol


This is the inside of the 8-bit counter. The 7-segment display stuff is taken straight from Sebastian's videos. The latch is just there to make sure that the second 4-bit counter only increments once the carry bit and the enable signal are high.

This is the inside of the 4-bit counters. I based it (to the best of my ability) on a 4-bit shift register, and then added the adders to make it count in binary instead of just shifting each bit up the chain. (I realised while writing this that I didn't need the d-latches in between the adders and flip-flops, so I removed them. I just can't be assed with taking a new screenshot lol)

I honestly have no idea if the flip-flops do what they're supposed to, since they don't really flip-flop, but I didn't understand any of the articles or posts I was reading, nor did the schematics translate well when I transfered them 1-to-1 into DLS so I just made do with what I had.

These are the flip-flop followed by the latch in case you were curious. :)

(+1)

The tinkering did reveal that the banding also changes every time I reload the chip, even when I don't change the tick speed. The tick speed and the chips used seem to have an effect on the kinds of bandings and other glitches that can occur, however.