so i've been trying to optimize my circuits for size alot, and i decided to try to optimize for speed a bit today and managed to make a much faster xor gate (3 ticks) by using wires with just 0 and 1 power (since the power decreases by 1 per tick)
this is planned as part of the upcoming signal analysis update where an oscilloscope will be introduced for things like this as well as handling metastability and whatnot.
i found the problem, i connected the inputs right to the first nand gate and 2nd and 3rd nand gates, and i also connected the 1st nand gate to the 2nd and 3rd nand gate and since a nand gate takes 1 tick those 2 paths take different amount of time