no it's a d latch since it doesn't only store on rising/falling edge of the clock signal as you can see in these images, the clock signal stays on (not falling/rising edge) but it still stores the value
ah yes! you seem to be right, my apologies! well done once again.
i would also like how difficult it is to deal with propagation delays in sequential circuits. i was thinking of adding an oscilloscope so that it is easier to view.
