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Digital Logic Sim

​A minimalistic digital logic simulator · By Sebastian Lague

NEW D LATCH DESIGN--

A topic by kshlok created 66 days ago Views: 243 Replies: 3
Viewing posts 1 to 2

This approach actually disables the randomization of the output at start! Let me know what you think @Sebastian Lague!

OK, I have found a bug: whenever I turn off the store signal, the output turns off. I don't know why that is, will check it out.

I actually just found out why: the simulation goes step-by-step. When the or gates output goes into the AND gate, the AND gate doesn't know its value and assumes its off. is there a way to fix this?

i fixed it: overwriting the multiplexer into its own chip fixes it