Hi, To be honest, managing multiple memory components and designing proper address decoding logic is a fundamental part of building any complex digital logic circuit. If handling, placing, and wiring 16 ROM chips is considered too tedious, boring, or overwhelming, then digital logic simulation and DLS might simply not be the right hobby for you. This discipline is all about building complex systems from basic blocks.
If you want to keep your main canvas clean, the proper way to handle this is by encapsulating those 16 ROMs and your decoding logic inside a single Subcircuit. You do it once, and you get a clean, reusable custom component with the exact capacity you need. Because of this, I highly doubt customizable or massive native ROM sizes will ever be added to DLS. There is simply no need for them when you can easily build them yourself using the components already available in the tool.