TL;DR - working as intended.
In real life, latches and flipflops start in an unknown state. In the simulation *some* style of latches and flip-flops (those built on cross-NOR and cross-NAND gates) also start in an unknown state. Within the simulation AND-NOT-OR style latches start in a known state. There's a bit more nuance to it, but that's the gist.
https://github.com/SebLague/Digital-Logic-Sim/issues/326
Just like in real life, you need some sort of asynchronous Clear signal during your Reset cycle to get the register to initialize to zero.