(RobMayer here) I spoke too soon in that github issue - I was wrong about the RS vs SR latches, sort of.
there's some nuance to it regarding both latch set/reset time asymmetry as well as race conditions brought on by simulation propagation. Some level of intersection of those two things is the source of counter-releated heartburn.
my full analysis is in this github issue (https://github.com/SebLague/Digital-Logic-Sim/issues/326) but the test results of latch set/reset asymmetry are detailed here specifically (https://github.com/SebLague/Digital-Logic-Sim/issues/326#issuecomment-2814708390) and some details about pre-latch and post-latch state race conditions here (https://github.com/SebLague/Digital-Logic-Sim/issues/326#issuecomment-2813148144)