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Digital Logic Sim

​A minimalistic digital logic simulator · By Sebastian Lague

Gates Delay? 1-tick buffer? 3+ Gates?

A topic by daemonaaspb created 1 day ago Views: 18
Viewing posts 1 to 1

good day, 1) i wander how to calculate time-delay of a chip

we only have a NAND gate for start, say it has delay 1, and so does NOT gate) AND gate, for example, contains NAND gate followed by NOT gate

does it mean it has delay 2, and so on?

2) i figured its important to make delays on control currencies the same

may we ask for 1-tick buffer gate to adjust delays? OR gate made of NAND has delay of 2

3) in a real chips, there is a multi-input AND and OR gates, made of connected in serial or parallel transistors it also has 1-tick delay

here, to make, say, 8-in AND gate (needed for fast adder, for example) we have to place 3 layers of gates, each delays 2, 6 total

may we ask for multi (or ajustable) input-AND and OR (or even NAND-NOR) gates?)

thanks for great app, just as i dreamed of)