No problem. 

Assuming you only have AND, and NOT gates; but also a NAND (an AND with the output put through a NOT gate).

With NANDS it can be done this way:

A through a NAND gate, fed into a another NAND gate (C)  with the other input of C being B put through a NAND gate; and the output of C being the output of the OR gate.

Here is a Diagram: