In the same day, I used the bus feature to make a full fledged 128bit DDR RAM. I call this DLSDDR1 technology for some reason XD
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By using a delayed NOT pulse, I managed to make a DDR (Double Data Rate) register.
The only change from the outside compared to the regular register is that it also saves on the falling edge of the clock. It uses a delayed NOT pulse (CLOCK => NOT => PULSE => NOT => PULSE => AND with CLOCK => NOT => AND with AND => REG-CLOCK). The DATA and STORE signals were not changed, but a PULSE was added to the regular CLOCK signal because without it, enabling both STORE and CLOCK would just cause the output to be synced with DATA.
This is a big leap for me, so now I can put DDR registers into my custom CPU, which I'm still figuring out the ALU (multiply and divide part) for.
What do you think?
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