So, mattzoglman, Rob Mayer and myself have noticed that there is an issue with chaining counters in this version.
We've tracked it down to a single-tick discrepancy in the time it takes for any NOR based, NAND based, or AND/NOT/OR based SR-latches to set and reset.
It's taking those latches one tick longer to set than it's taking them to reset, and in my case this caused issues where the zero-check I perform in my counter to trigger the carry signal would give false positives every time the next-most significant bit was turned on, as all the less significant bits would turn off a single tick earlier, causing the wires to read a zero for a split-second.
Thankfully, with some help from KatIsBackKathTorio on discord, Rob identified a workaround; Use RS latches instead of SR latches for your registers.
Hopefully this helps!