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OK. Can you perform the operation I described above in those simulators? Ie. With 16-bit words, write only 1 of the 2 word bytes on the next clock tick? 

Looking at Logisim help pages (http://www.cburch.com/logisim/docs/2.7/en/html/libs/mem/ram.html), if I understood correctly, you can only store whole words when ld=0. So in order to write only (e.g.) the 2nd byte of 16-bit word, you have to first read the word into a register, replace the 2nd byte's value and store the new 16-bit word into the SRAM. Which in turn means that you need at least 3 clock cycles.

With separate write enable signals for each word byte, as in DLS, you can do it on a single clock cycle.

I don't think the operation can be done on 1 clock cycle .