i think i understand it better but the concrete example would be welcomed.
I was thinking of creating a demo circuit for you to try out the various combinations or draw some diagrams but it'll take some time. Until then please take a look at this in case it helps a bit more: https://www.ece.cmu.edu/~ece548/localcpy/sramop.pdf
If I understood correctly, what you expected to see was an 1-bit write enable input independent of the word width. Am I correct?
You are indeed correct.That's how RAM components are designed in other softwares i use, like logisim or logiccircuit.
OK. Can you perform the operation I described above in those simulators? Ie. With 16-bit words, write only 1 of the 2 word bytes on the next clock tick?
Looking at Logisim help pages (http://www.cburch.com/logisim/docs/2.7/en/html/libs/mem/ram.html), if I understood correctly, you can only store whole words when ld=0. So in order to write only (e.g.) the 2nd byte of 16-bit word, you have to first read the word into a register, replace the 2nd byte's value and store the new 16-bit word into the SRAM. Which in turn means that you need at least 3 clock cycles.
With separate write enable signals for each word byte, as in DLS, you can do it on a single clock cycle.