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I just took a look at the manual and you are right, it's not clear enough.

SRAMs in DLS are word-addressable memories. If your word size is larger than 8 bits (Din width greater than 8) you have more than 1 byte per word. \bwe is an active low signal controlling which bytes of the addressed word will be written (bwe = byte write enable). 

E.g. if your word size is 16 bits and you address size is 8 bits, it means that you have 256 words or 512 bytes. But since you can only access individual words (i.e. byte pairs) you can only read or write bytes starting at even addresses. What would you do if you wanted to write only byte #5 which is the 2nd byte of the 3rd word? You should set the inputs to the following values:

  • addr = 02h
  • Din = XX12h, where XXh can be any value (SRAM should not care)
  • \bwe = 10b

This way, on the next rising edge of clk, only the 2nd byte of the 3rd word will be overwritten, leaving the 1st byte intact.

Hope it clears things up a bit. If not, I'll try a more concrete example.

i think i understand it better but the concrete example would be welcomed.

I was thinking of creating a demo circuit for you to try out the various combinations or draw some diagrams but it'll take some time. Until then please take a look at this in case it helps a bit more:

If I understood correctly, what you expected to see was an 1-bit write enable input independent of the word width. Am I correct?

You are indeed correct.That's how RAM components are designed in other softwares i use, like logisim or logiccircuit.

OK. Can you perform the operation I described above in those simulators? Ie. With 16-bit words, write only 1 of the 2 word bytes on the next clock tick? 

Looking at Logisim help pages (, if I understood correctly, you can only store whole words when ld=0. So in order to write only (e.g.) the 2nd byte of 16-bit word, you have to first read the word into a register, replace the 2nd byte's value and store the new 16-bit word into the SRAM. Which in turn means that you need at least 3 clock cycles.

With separate write enable signals for each word byte, as in DLS, you can do it on a single clock cycle.

I don't think the operation can be done on 1 clock cycle .