> I must check it on my i7-4790k, currently I'm using it on notebook with i5, but I have access to dual Xeon workstation, it would be funny to check performance on it ;)
Unfortunately, the dual Xeons won't make a difference in performance. Currently simulation is single threaded and only 8ms of frame time is devoted to it. Until I manage to move the simulation to a separate thread and it ends up being faster than the single threaded version, 8ms should be enough for smooth interaction with the schematic.
> PS: new idea - pull-up resistors. Sometimes when you use tri-state buffers you want 0 instead of "Z" (not connected state)
Aren't pull-up resistors considered analog devices (i.e. they require a Vcc or Gnd pin to work)? If yes, they don't fit into the current simulator.
Can you describe a situation where a tri-state buffer with a 0 instead of Z output would be required? The only reason there are tri-state buffers in DLS is to be able to support buses (which are effectively wire-OR structures). Is there another usage for them? Isn't it possible to use AND/OR gates in places where you need a tri-state buffer with 0 disconnected state?